>>More or less. Context switching in the Pentium Processor family and later got a good deal more complicated when the MMX instruction set was introduced; the same registers stored by the TCB structure can contain either MMX-related values or FPU-related values, and a number of the system registers have bit patterns that mean something in one of the modes, but not in both. If VFP tries to do something with the registers in an inconsistent state, even as simple as loading a value from memory to a register, CPU fall down go boom...
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>>The MMX instruction set complicates things because the same registers used for MMX operations are also the floating point registers. Some of the setups that might be valid for a processor in MMX mode are verboten in MMX mode, and vice versa. The automatic actions built into the processor for reading state information from a TCB on a task switch didn't make allowance for that in many cases; the assumption was that the processor would handle things automagically. Unfortunately, someone dented the magic wand.
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>>_fpreset() sets the floating point registers to a consistent state (and as I recall, clears them, too.) If you reset the FPU to a consistent state, then floating point operations don't die a gruesome and ugly death when they get invoked.
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>Just one comment, "Wow". I didn't expect such an in depth explanation, Ed, but thanks. I know more now about MMX than I did before. Don't the PIIs and P3s all have MMX (they just don't advertise it like they used to). I do know that the P3s have some additional stuff, but can't recall exactly what it is. I believe that there's a second FPU involved and I assume that the same would apply.

Yep. Intel introduced the MMX instruction set way back with the Pentium MMX chip, aka the P-55. All the Intel processor since then have at least the MMX instruction set added to them; that's the Celerons, Pentium II, Pentium III and the Xeons 9as of Friday, there are now 550MHz PIII Xeons out in the world, and 500MHz units with up to 2MB of L2 cache running at core speed.

The PIII introduced about 70 new processor instructions to the processor. 8 large (128 bit registers were added which allow greater parallelism in execution, a second floating point pipeline and some SIMD processing (some of the new FP instructions can execute in parallel on multiple data items.) These new KNI/SSE instructions are largely targeted at graphics and audio, although they'll affect anything that does significant amounts of floating point computation and can be optimized to use the new instruction set. These instructions are close in concept to the added instructions in the K6-3D and upcoming K7 processors from AMD; a number of game vendors and a couple of CAD vendors have started coding drivers to take advantage of the new instruction sets, and the K6-3DNow extensions have been in the pipe longer, so there is already some support for them. A good reference site for tis, where the SSE and 3DNow! instructions are compared, and a good general source of information on processors and chipsets in general is Tom's Hardware Page.